Science and Technology

This paper proposes a novel approach for resource- and reconfiguration- aware floorplanning. Different from existing approaches, our floorplanning algorithm takes specific physical constraints such as resource distribution and the granularity of reconfiguration possible for a given FPGA device into account. These physical constraints are typically considered at the later placement stage. In order to emphasize this fundamental difference with respect to traditional floorplanners, we refer to our approach as a floorplacer. Different aspects of the problems have been described, focusing particularly on the FPGA’s resource heterogeneity and the temporal dimension typical of reconfigurable systems. Once the problem is introduced a comparison among related works has been provided and their limits have been pointed out. Our proposed approach specifically considers the feasibility of the associated communication infrastructure for a given floorplan. Experimental results proved the validity of the proposed approach.

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A. Montone, D. Sciuto, M. D. Santambrogio, S. Memik, Placement and Floorplanning in Dynamically Reconfigurable FPGAs, ACM Transaction on Reconfigurable Technology and Systems, 2010, Vol. 3, N. 4

Abstract
The proposed work aims at identifying groups of Reconfigurable Functional Units that are likely to be configured in the same chip area, identifying these areas based on resource requirements, device capabilities and wirelength. The proposed floorplacement framework, tailored for Xilinx Virtex 4 and 5 FPGAs, uses an objective function based on external wirelength, i.e., the estimated length of the nets connecting each Reconfigurable Functional Unit to the corresponding required chip Input Output Blocks. The proposed approach results, as also demonstrated in the experimental results section, in a shorter external wirelength (an average reduction of 50%) with respect to purely area-driven approaches and a highly increased probability of re-use of existing links (90% reduction can be obtained in the best case).

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A. Montone, D. Santambrogio, D. Sciuto, Wirelength driven floorplacement for FPGA-based partial reconfigurable systems, to appear in Proceedings of IEEE Reconfigurable Architecture Workshop, 2010
 

Abstract
Aim of this paper is to propose a Reconfigurable Processing Element based on a Harvard Architecture, called HARPE. HARPE’s architecture includes a MicroBlaze soft-processor in order to make HARPEs deployable also on devices not having processors on silicon die. In such a context, this work also introduces a novel approach for the management of processor data memory. The proposed approach allows the individual management of data and the dynamic update of the memory, thus making it possible to define Partially Dynamical Reconfigurable Multi Processing Element Systems, that consist of several master (e.g., soft-processors, hard-processors or HARPE cores) and slave components. Finally, the proposed methodology enables the possibility of creating a system in which both HARPEs and their memo- ries (data and code) can be separately configured at run time with a partial configuration bitstream, in order to make the whole system more flexible with respect to changes occurring in the external environment.

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A. Montone, V. Rana, M. D. Santambrogio, D. Sciuto, HARPE: a Harvard-based Processing Element Tailored for Partial Dynamic Reconfigurable Architectures, IEEE Reconfigurable Architecture Workshop, 2008