Abstract
The proposed work aims at identifying groups of Reconfigurable Functional Units that are likely to be configured in the same chip area, identifying these areas based on resource requirements, device capabilities and wirelength. The proposed floorplacement framework, tailored for Xilinx Virtex 4 and 5 FPGAs, uses an objective function based on external wirelength, i.e., the estimated length of the nets connecting each Reconfigurable Functional Unit to the corresponding required chip Input Output Blocks. The proposed approach results, as also demonstrated in the experimental results section, in a shorter external wirelength (an average reduction of 50%) with respect to purely area-driven approaches and a highly increased probability of re-use of existing links (90% reduction can be obtained in the best case).

 Abstract
Aim of this paper is to propose a Reconfigurable Processing Element based on a Harvard Architecture, called HARPE. HARPE’s architecture includes a MicroBlaze soft-processor in order to make HARPEs deployable also on devices not having processors on silicon die. In such a context, this work also introduces a novel approach for the management of processor data memory. The proposed approach allows the individual management of data and the dynamic update of the memory, thus making it possible to define Partially Dynamical Reconfigurable Multi Processing Element Systems, that consist of several master (e.g., soft-processors, hard-processors or HARPE cores) and slave components. Finally, the proposed methodology enables the possibility of creating a system in which both HARPEs and their memo- ries (data and code) can be separately configured at run time with a partial configuration bitstream, in order to make the whole system more flexible with respect to changes occurring in the external environment.

Abstract

This paper aims at introducing a novel approach for the management of processor data memory in reconfigurable systems. The proposed approach allows the individual management of separated data and the dynamic update of the memory with a partial bitstream. By following this way it is possible to create a system in which several master components (e.g., soft-processors or hard-processors) can be dynamically configured and in which their memory can be dynamically changed. In the first section the reconfigurable scenario and its problems concerning to memory management will be introduced. The following sections will describe the state of the art and the development details of the tool that implements the proposed approach. Finally, a set of experimental results will be presented and conclusive remarks will be drawn.